54ACT377 flip-flop equivalent, octal d flip-flop.
n ICC reduced by 50%
Logic Symbols
IEEE/IEC
DS100290-1
DS100290-2
Pin Names D0
–D7 CE Q0
–Q7 CP
Description Data Inputs Clock Enable (A.
n Clock enable for address and data synchronization applications n Eight edge-triggered D flip-flops n Buffered common c.
The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The.
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